The present invention relates generally to integrated circuits, and more particularly to methods for fabricating integrated circuits. Still more particularly, the present invention relates to methods for forming fully silicided gate electrodes while also providing unsilicided resistors.
As technology becomes more advanced, the design of integrated circuits (ICs) becomes more complicated. To further increase performance and reduce cost, improvements to the structural design of the IC as well as the processing methods to fabricate the ICs are of paramount importance. For example, scaling to lower gate oxide thickness to achieve higher gate capacitance is required as transistor channel lengths are decreased in order for the gate electrode to maintain control of the channel. In doped poly-silicon gate electrodes, the finite solubility of dopant atoms places a lower limit on gate resistance and leads to the formation of a finite thickness space charge layer depleted of free charge carriers at the gate electrode/oxide interface. This insulating poly-depletion layer increases the effective oxide thickness, decreasing overall gate capacitance, and poses a severe limitation to device scaling.
Replacing the poly-silicon gate electrode with a metal gate electrode relieves the problem of poly-depletion due to the high carrier concentration available in the metal. However, metal gates face numerous challenging process integration issues including metal etch process development, thermal budget constraints, and metal contamination. One attractive option is to alloy a metal with a conventionally patterned poly-silicon gate electrode in its entirety to form a fully silicided gate electrode. Since conventional IC processes already rely on a single silicide formation process to concurrently fabricate contacts to poly gate electrodes and source/ drains, a fully-silicided gate can potentially be integrated with minimal process modification.
In conventional IC fabrication, silicide contacts to the source/drains and the doped poly-silicon gate electrodes are formed after source/drain implants are annealed and before deposition of device passivating dielectric layer. Sputter deposition of a blanket metal film is followed by a thermal process to react the metal with exposed silicon areas on the wafer forming silicide contacts to the source/drain and the gate electrode. Since the source/drain silicide contact depth must be minimized to prevent excess junction leakage and the poly-silicon gate electrode is typically thicker than the depth of the source/drain silicide contact, only the top portion of the poly-silicon gate electrode is silicided. Excess unreacted metal including metal deposited on dielectric spacers and isolation is then removed by a wet etch. Since only areas with exposed silicon are silicided, the process is self-aligned, and often referred to as a salicide process.
The primary process modification required to form an IC with fully-silicided gate electrodes is to maintain shallow the source/drain silicide contacts while achieving full-silicidation of the gate electrodes. One method of decoupling source/ drain silicidation from full gate silicidation is to perform the conventional silicidation followed by an additional silicidation of the gate alone. To prevent additional silicidation of the source/drains, the second silicidation is performed after dielectric layers are blanket deposited to passivate the source/drains and polished back to expose only the gate electrode.
In a conventional IC process the same doped poly-silicon layer used to form the gate electrode also serves to form poly silicon resistors which are of high value for various circuit designs. The resistivity of silicided polysilicon is substantially lower than that of un-silicided doped polysilicon, therefore it is desirable to use un-silicided doped polysilicon in order to minimize the chip surface area required to accommodate a resistor of a given resistor. In the conventional IC process, this is achieved by patterning an additional dielectric layer after source/drain implant and before silicidation in order to protect the polysilicon resistors from silicidation. In the full silicidation process, since there are two silicidation steps, additional measures must be taken to prevent silicidation of polysilicon resistors. As such, desirable in the art of IC fabrication are additional structural designs and processing methods that may enable and simplify concurrent formations of fully silicided gate electrodes and high resistance poly-silicon resistors.